Hierarchical performance estimation of analog blocks using pareto fronts

Abstract

This paper presents a general approach for hierarchical performance estimation (PE) of any analog system. Not only PE is evaluated by the extracted Pareto Fronts (PF) but also an approximate design of the system is obtained. PE of an analog system requires a well-determined performance design space (PDS) exploration for a given technology. PF which is a very useful technique for evaluating the performance space, provides the set of all optimal trade-offs of competing performances of a given block. Thus, the designer can easily get insight into the capability of the system. In this work, a three-level system is divided into its subsystems and PF of each subsystem is determined. Then, hierarchical methodology of PF composition is applied from lower levels to higher levels so the PF of the main system is obtained with less computational effort. The novelty of the work lies on using simple algorithms instead of complex optimization algorithms and simulation loops.