A CMOS classifier circuit using neural networks with novel architecture

Abstract

In this letter, complementary metal–oxide–semiconductor (CMOS) implementation of a neural network (NN) classifier with several output levels and a different architecture is given. The proposed circuit operates in current mode and can classify several types of data. The classifier circuit is designed using a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using a 0.35- um TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results.