Linearly weighted classifier circuit
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IEEE
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info:eu-repo/semantics/closedAccess
Özet
In this paper a CMOS realization of a linearly weighted classifier circuit which is called classifier block is proposed. The proposed classifier block is composed of linearly weighted circuits (LWC) and CMOS core circuits (CC). The proposed circuit can classify linearly non-separable data. The weights of the classifier circuit are achieved with LWC blocks. Using 0.35 mum AMS technology parameters, SPICE simulation results for a LWC and classifier block are included to verify the expected results.
Açıklama
Yıldız, Merih (Dogus Author), Minaei, Shahram (Dogus Author) -- Full conference title: 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference : (NEWCAS-TAISA 2009) ; Toulouse, France, 28 June - 1 July 2009
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CMOS Integrated Circuits, Linear Network Analysis
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2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference : (NEWCAS-TAISA 2009)
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Yıldız, M., Minaei, S., & Özoğuz, S. (2009). Linearly weighted classifier circuit. In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference : (NEWCAS-TAISA 2009) (4p). Piscataway, NJ: IEEE https://dx.doi.org/10.1109/NEWCAS.2009.5290438
