CMOS realization of a quantized-output classifier circuit
Citation
Yıldız, M., Minaei, S., and Göknar, İ. C. (2006). CMOS realization of a quantized-output classifier circuit. In 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06, (pp. 292-295). Piscataway, NJ: IEEE. https://dx.doi.org/10.1109/ICECS.2006.379783Abstract
In this paper a CMOS implementation of a multi-input data classifier with several output levels and a different architecture is presented. The proposed circuit operates in current-mode and can classify several types of analog vector data. The classifier circuit’s new architecture consists of the interconnections of core cells each possessing a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using 0.35µm TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results.
