Neural CMOS - integrated circuit and its application to data classification
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CitationGöknar, İ. C., Yıldız, M., Minaei, S., & Deniz, E. (2012). Neural CMOS - integrated circuit and its application to data classification. IEEE Transactions on Neural Networks and Learning Systems, 23(5), 717-724. https://dx.doi.org/10.1109/TNNLS.2012.2188541
Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.