A CMOS classifier circuit using neural networks with novel architecture
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CitationYıldız, M., Minaei, S., and Göknar, İ. C. (2007). A CMOS classifier circuit using neural networks with novel architecture. IEEE Transactions on Neural Networks, 18(6), 1845-1850. https://dx.doi.org/10.1109/TNN.2007.902961
In this letter, complementary metal–oxide–semiconductor (CMOS) implementation of a neural network (NN) classifier with several output levels and a different architecture is given. The proposed circuit operates in current mode and can classify several types of data. The classifier circuit is designed using a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using a 0.35- um TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results.