Hybrid approach for performance estimation; embedded tool for analog design automation systems

Abstract

A novel approach for performance estimation is described which gives the designer access to the design space boundaries of a circuit topology so that the tradeoff analysis of competing performances can be evaluated by optimum design points and Pareto curves with an acceptable execution time and transistor-level accuracy can be obtained. Recently, there is a strong emphasis on numerical techniques for performance estimation models however neither of them satisfies the following three significant issues; accuracy, time-consumption and topology-independent modeling. This new approach allows using different performance estimation methods together in order to speed up the overall design automation system with an acceptable time and accuracy for any given topology.