Time delay calculation in current-mode circuits
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CitationKurnaz, M., Minaei, S., & Göknar, İ. C. (2013). Time delay calculation in current-mode circuits. In 8th International Conference on Electrical and Electronics Engineering (ELECO), (pp. 349-352). Piscataway, NJ: IEEE. http://dx.doi.org/10.1109/ELECO.2013.6713859
In this paper time delay calculations for a current-mode circuit are considered and an equivalent circuit model for delay estimation is developed. The relation obtained for the time delay can be adapted to any CMOS current-mode circuit. The proposed calculation method is verified with SPICE using 0.35 mu m TSMC MOSIS technology parameters.